1. Field of the Invention
The present invention relates to a design data processing method and a recording medium, in particular, to a design data processing method and a recording medium for design data obtained from designing an LSI (Large Scale Integrated) circuit for each rank of hierarchy in macro unit.
Recently, design of LSI circuit is made, in general, in such a manner that a layout of circuit is made hierarchically, macros being produced/created. In such a layout method, layouts between macros and between ranks of hierarchy are not easy to recognize. Accordingly, a layout method in which layouts between macros and between ranks of hierarchy can be efficiently recognized is demanded.
2. Description of the Related Art
In a hierarchical layout method of LSI circuit in the prior art, a design is made from a lower rank of hierarchy, in order, ordinarily. Thereby, when the same wiring layer is employed by an upper rank and a lower rank of hierarchy commonly, a design is made by a bottom-up manner. The layout method by the bottom-up manner is a method in which, when a layout of an upper rank of hierarchy is made, a lower rank of hierarchy is referred to.
In the hierarchical layout method in the related art, there is a limitation that no same wiring region is commonly used by an upper rank and a lower rank of hierarchy.
FIG. 1 illustrates one example of a wiring method between macros in the related art.
A layout structure 1 of a rank Ln of hierarchy in the related art includes macro blocks B1 through B8. When the macro block B1 and macro block B2 are connected to one another, a wire 2 is disposed in a manner such as to avoid the macro block B3 (corresponding to a wiring region of the lower rank of hierarchy) as shown in FIG. 1 due to the above-mentioned limitation on layout.
Further, in the hierarchical layout method in the related art, when a layout is made for an upper rank of hierarchy while the layout of lower rank of hierarchy is being displayed, wiring is inhibited for the lower rank of hierarchy. Only wiring to terminals for connecting macro blocks externally can be made.
FIG. 2 illustrates one example of a display of macro terminals in the related art.
An upper rank Ln of hierarchy has a macro block B0. The macro block Ln includes macro blocks B1 through B4. A lower rank Ln−1 of hierarchy has wires 3-1 through 3-8 disposed therein for connecting the periphery of the macro block B0 of the upper rank Ln externally.
In this case, when a layout is made for the upper rank Ln, wiring for the lower rank Ln−1 is inhibited. However, because the wires 3-1 through 3-8 have external wires connected thereto, terminals T1 through T8 are displayed at portions of the upper rank Ln corresponding to the wires 3-1 through 3-8. At this time, only wiring of portions of the terminals T1 through T8 is allowed.
Further, in the hierarchical layout method in the related art, there is a limitation of metal density due to characteristics of semiconductor. The limitation of metal density is a limitation in that, when a layout of metal of wires or the like is made, a ratio of an area occupied by the metal in a predetermined area is not larger than a predetermined value. In order to check this limitation, metal density rule check is performed in the hierarchical layout method in the related art.
FIG. 3 illustrates a method of metal density rule check in the related art.
In the metal density rule check, first, a layout region 4 is divided into a plurality of regions A11 through Amn each having a predetermined area S0. Then, each region of the regions A11 through Amn is extracted in sequence. Then, the area of the metal portion of the wires L1, L2 and L3 included in the extracted region is calculated.
Then, the metal density that is a ratio of the metal portion occupied in the region is obtained. For example, in the region A22, {(W1+W2)/S0}×100 (%); and in the region Am1, {(W3+W4)/S0}×100 (%). According to the metal density rule, it is prescribed that the metal density should be not more than 80%. When the metal density is more than 80%, it is determined that a metal density error is detected, and correction of the layout is required.
In this case, it is not possible to recognize the metal density rule at the time of the layout being originally made.
Further, in the layout method in the related art, a parallel line length is checked. The parallel line length check is a check made for detecting a noise error.
FIG. 4 illustrates a method of parallel line length check in the related art.
In FIG. 4, a wire 5-1 is a wire connecting a macro block B1 to a macro block B2, while a wire 5-2 is a wire connecting the macro block B1 to a macro block B3.
In the parallel line length check, the section L1 through which the wire 5-1 and wire 5-2 are parallel to one another is detected. When the section L1 is longer than a predetermined line length, it is determined that the amount of noise generated from an adjacent line is larger than a prescribed value, and, thus, it is determined that a noise error is detected.
Thus, in the layout method in the related art, the layout by the bottom-up manner is employed as described above in which a layout of a lower rank of hierarchy is referred to when a layout for an upper rank of hierarchy is made. Accordingly, when the layout for the lower rank is to be modified after the layout for the upper rank is made, it is not possible to refer to a wiring state and so forth of the upper rank of hierarchy. Therefore, the efficiency in layout is not satisfactory.
Further, in the layout method in the related art, as described above, when a macro block is connected externally, wiring in an inside periphery of the macro block is inhibited, only terminals are displayed at portions to be connected externally, and wires in the inside periphery of the macro block are not displayed. Accordingly, when a layout of wiring in an outside periphery of the macro block is made, it is not possible to examine separations between the external wires and internal wires of the macro block. Therefore, it is not possible to make layout of wires in consideration of influence between external and internal wires.
Further, recently, a density of wires has been increased, and the metal density rule has been severely applied. However, the metal density rule check is made after an original layout of all wires is made, and, therefore, it is not possible to make an original layout in consideration of the metal density rule. Thereby, the efficiency in layout is not satisfactory.
Further, because the detection of noise error is made from the parallel line length, wiring which does not actually result in a noise error is determined to cause a noise error. Therefore, a designer should check manually whether or not wiring determined to cause a noise error actually cause a noise error. Thereby, an enormous labor and time are required for a layout of wiring.
Further, in the related art, when a macro block includes a vacant space, because it is not allowed to dispose another macro block in one macro block, the vacant space remains as a useless space. This obstructs high-density integration of LSI circuit.